Dynamic random access memory (DRAM) integrated circuit arrays have existed for more than thirty years and their dramatic increase in storage capacity has been achieved through advances in semiconductor fabrication technology and circuit design technology. The tremendous advances in these two technologies have also achieved higher levels of integration that permit dramatic reductions in memory array size and cost, as well as increased process yield.
FIG. 1 is a schematic diagram of a DRAM memory cell 100 comprising an access transistor 101 and a capacitor 102. The capacitor 102, which is coupled to a Vcc/2 potential source and the transistor 101, stores one bit of data in the form of a charge. Typically, a charge of one polarity (e.g., a charge corresponding to a potential difference across the capacitor 102 of +Vcc/2) is stored in the capacitor 102 to represent a binary “1” while a charge of the opposite polarity (e.g., a charge corresponding to a potential difference across the capacitor 102 of −Vcc/2) represents a binary “0.” The gate of the transistor 101 is coupled to a word line 103, thereby permitting the word line 103 to control whether the capacitor 102 is conductively coupled via the transistor 101 to a bit line 104. The default state of each word line 103 is at ground potential, which causes the transistor 101 to be switched off, thereby electrically isolating capacitor 102.
One of the drawbacks associated with DRAM cells 100 is that the charge on the capacitor 102 may naturally decay over time, even if the capacitor 102 remains electrically isolated. Thus, DRAM cells 100 require periodic refreshing. Additionally, as discussed below, refreshing is also required after a memory cell 100 has been accessed, for example, as part of a read operation.
FIG. 2 illustrates a memory device 200 comprising a plurality of memory arrays 150a, 150b. (Generally, in the drawings, elements having the same numerical value are of the same type. For example, sense amplifiers 300a and 300b in FIG. 2 have identical circuitry to sense amplifier 300 of FIG. 3. A lower case alphabetic suffix is generally used to discriminate between different units of the same type. However, upper case prefixes, such as “N” and “P” may denote different circuitry associated with negative or positive typed variants.) Each memory array 150a, 150b includes a plurality of memory cells 100a-100d, 100e-100h arranged by tiling a plurality of memory cells 100 together so that the memory cells 100 along any given bit line 104a, 104a′, 104b, 104b′ do not share a common word line 103a-103d. Conversely, the memory cells 100 along any word line 103 do not share a common bit line 104a, 104a′, 104b, 104b′. Each memory array has its own set of bit lines. For example, memory array 150a includes bit lines 104a, 104b, while memory array 150b includes bit lines 104a′, 104b′. The bit lines from each adjacent pair of memory arrays 150a, 150b are coupled to a common sense amplifier 300a, 300b. For example, bit lines 104a, 104a′ are coupled to sense amplifier 300a, while bit lines 104b, 104b′ are coupled to sense amplifier 300b. As explained below, the sense amplifiers 300a, 300b are used to conduct the sense/refresh portion when a memory cell 100a-100h is read.
Reading a DRAM memory cell comprises the operations of accessing and sensing/refreshing.
The purpose of the access operation is to transfer charge stored on the capacitor 102 to the bit line 104 associated with the memory cell 100. The access operation begins by precharging each bit line 104a, 104a′, 104b, 104b′ to a predetermined potential (e.g., Vcc/2) by coupling each bit line 104a, 104b to a potential source (not illustrated). Each bit line 104a, 104b is then electrically disconnected. The bit lines 104a, 104a′, 104b, 104b′ will float at the predetermined potential due to the inherent capacitance of the bit lines 104a, 104a′, 104b, 104b′. Subsequently, the word line (e.g., 103a) associated with a memory cell being read (e.g., 100a) is activated by raising its potential to a level which causes each transistor 101a, 101e coupled to the word line 103a to gate. It should be noted that due to inherent parasitic capacitance between bit lines 104 and word lines 103, activation of a word line 103 will cause the potential at each associated bit line 104 to increase slightly. However, in typical DRAM systems, the magnitude of this potential change is insignificant in comparison to the magnitude of the potential change on the bit lines due to charge sharing. Therefore, with respect to DRAM systems only, further discussion regarding the effect of parasitic capacitance is omitted.
Activation of the word line 103a causes each capacitor 102a, 102e of each memory cell 100a, 100e coupled to that word line 103a to share its charge with its associated bit line 104a, 104b. The bit lines 104a′, 104b′ in the other array 150b remain at the pre-charge potential. The charge sharing causes the bit line 104a, 104b potential to either increase or decrease, depending upon the charge stored in the capacitors 102a, 102e. Since only the bit lines 104a, 104b of one memory array has its potential altered, at each sense amplifier 300a, 300b, a differential potential develops between the bit lines 104a, 104b associated with the activated word line 103a and the other bit lines 104a′, 104b′ associated with the same sense amplifier 300a, 300b. Thus, the access operation causes the bit lines 104a, 104b associated with the cell 100a being read to have a potential which is either greater than or less than the pre-charged voltage. However, the change in potential is small and requires amplification before it can be used.
The sense/refresh operation serves two purposes. First, the sense/refresh operation amplifies the small change in potential to the bit line coupled to the cell which was accessed. If the bit line has a potential which is lower than the pre-charge potential, the bit line will be driven to ground during sensing. Alternatively, if the bit line has a potential which is higher than the pre-charge potential, the bit line will be driven to Vcc during sensing. The second purpose of the sense/refresh operation is to restore the state of the charge in the capacitor of the accessed cell to the state it had prior to the access operation. This step is required since the access operation diluted the charge stored on the capacitor by sharing it with the bit line.
FIG. 3 is a detailed illustration of a sense amplifier 300, which comprises a N-sense amp 310N and a P-sense amp portion 310P. The N-sense amp 310N and the P-sense amp 310P include nodes NLAT* and ACT, respectively. These nodes are coupled to controllable potential sources (not illustrated). Node NLAT* is initially biased to the pre-charge potential of the bit lines 104 (e.g., Vcc/2) while node ACT is initially biased to ground. In this initial state, the transistors 301-304 of the N- and P- sense amps 310N, 310P are switched off. The sense/refresh operation is a two phased operation in which the N- sense amp 310N is triggered before the P- sense amp 310P.
The N- sense amp 310N is triggered by bringing the potential at node NLAT* from the pre-charge potential (e.g., Vcc/2) towards ground potential. As the potential difference between node NLAT* and the bit lines 104a, 104a′, 104b, 104b′ approach the threshold potential of NMOS transistors 301, 302, the transistor with the gate coupled to the higher voltage bit line begins to conduct. This causes the lower voltage bit line to discharge towards the voltage of the NLAT* node. Thus, when node NLAT* reaches ground potential, the lower voltage bit line will also reach ground potential. The other NMOS transistor never conducts since its gate is coupled to the low voltage digit line being discharged towards ground.
The P- sense amp 310P is triggered (after the N- sense amp 310N has been triggered) by bringing the potential at node ACT from ground towards Vcc. As the potential of the lower voltage bit line approaches ground (caused by the earlier triggering of the N- sense amp 310N), the PMOS transistor with its gate coupled to the lower potential bit line will begin to conduct. This causes the initially higher potential bit line to be charged to a potential of Vcc. After both the N- and P- sense amps 310N, 310P have been triggered, the higher voltage bit line has its potential elevated to Vcc while the lower potential bit line has it potential reduced to ground. Thus, the process of triggering both sense amps 310N, 310P amplifies the potential difference created by the access operation to a level suitable for use in digital circuits. In particular, the bit line 104a associated with the memory cell 100a being read is driven from the pre-charge potential of Vcc/2 to ground if the memory cell 100a stored a charge corresponding to a binary 0, or to Vcc if the memory cell 100a stored a charge corresponding to a binary 1, thereby permitting a comparator (or differential amplifier) 350a coupled to bit lines 104a, 104a′ to output a binary 0 or 1 consistent with the data stored in the cell 100a on signal line 351. Additionally, the charge initially stored on the capacitor 102a of the accessed cell is restored to its pre-access state.
Efforts continue to identify other forms of memory elements for use in memory cells. Recent studies have focused on resistive materials that can be programmed to exhibit either high or low stable ohmic states. A programmable resistance element of such material could be programmed (set) to a high resistive state to store, for example, a binary “1” data bit or programmed to a low resistive state to store a binary “0” data bit. The stored data bit could then be retrieved by detecting the magnitude of a readout current switched through the resistive memory element by an access device, thus indicating the stable resistance state it had previously been programmed to.
Recently chalcogenide glasses fabricated with solid electrolyte such as a metal doped chalcogenide have been investigated as data storage memory cells for use in memory devices, such as DRAM memory devices. U.S. Pat. Nos. 5,761,115, 5,896,312, 5,914,893, and 6,084,796 all describe this technology and are incorporated herein by reference. The storage cells are called programmable conductor cells (alternatively, they are also known as programmable metallization cells). One characteristic of such a cell is that it typically includes solid metal electrolyte such as a metal doped chalcogenide and a cathode and anode spaced apart on a surface of the fast ion conductor. Application of a voltage across the cathode and anode causes growth of a metal dendrite which changes the resistance and capacitance of the cell which can then be used to store data.
One particularly promising programmable, bi-stable resistive material is an alloy system including Ge:Se:Ag. A memory element comprised of a chalcogenide material has a natural stable high resistive state but can be programmed to a low resistance state by passing a current pulse from a voltage of suitable polarity through the cell. This causes a programmable conductor, also known as a dendrite, to grow between the anode and cathode which lowers the cell resistance. A chalcogenide memory element is simply written over by the appropriate current pulse and voltage polarity (reverse of that which writes the cell to a low resistance state) to reprogram it, and thus does not need to be erased. Moreover, a memory element of chalcogenide material is nearly nonvolatile, in that it need only be rarely (e.g., once per week) connected to a power supply or refreshed, in order to retain its programmed low resistance state. Such memory cells, unlike DRAM cells, can be accessed without requiring a refresh.
While conventional sense amp circuitry, such as those associated with DRAM cells, are capable of sensing programmable conductor random access memory (PCRAM) cells, the natural refresh operation associated with these sense amplifiers are not required in a PCRAM context. Indeed, frequent rewriting of PCRAM cells is not desirable because it can cause the PCRAM cell to become resistant to rewriting. Accordingly, there is a need and desire for a circuit and method for reading PCRAM cells without refreshing them.